8000 `sgemm`: write the operand addresses so GCC will strength-reduce them on aarch64 by femelo · Pull Request #1603 · ggml-org/ggml · GitHub
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sgemm: write the operand addresses so GCC will strength-reduce them on aarch64 - #1603

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femelo:feature/write-operand-addresses-to-avoid-re-derivation-on-aarch64

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@femelo
@femelo femelo commented Aug 21, 2026 •
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Problem. gemm_bloc addresses its operands as A + lda * (ii + i) + l against the class members.
On aarch64, GCC 14.2 does not form pointer induction variables over l from that: it re-derives all
seven operand addresses every iteration — 8 add + 6 lsl wrapped around 12 fmla and 7 ldr q, a
35-instruction loop where 21 do the same work. The identical source with the bases and strides as
locals compiles to those 21, with the same compiler and the same flags (checked by compiling the
extracted block with ggml's own flags.make line).

Fix. Hoist the two base pointers and the strides into locals before the loop. No arithmetic change
whatsoever — bit-identical output, and it is an addressing rewrite, not a numerical one.

Evidence. With PR #1602 also applied: 22.0 → 25.1 GFLOP/s at the eleven shapes, 4 threads.

Why it is scoped to aarch64. x86-64 does not want it: there GCC already forms the induction
variables, and the extra live values only add pressure — 55.4 → 53.6 GFLOP/s and 12 more %rsp
reads in the block. With the #if defined(__aarch64__) in place, the x86 object code is
register-renaming-identical to the current one, which is a better check than re-timing it. clang on
aarch64 is neutral (24.0 vs 23.8), since it already did this.

This is in the context of a new ggml-based engine targeting edge devices called loom.cpp. The optimization was derived from multiple iterations with Claude Code trying to close the gap for the same model against onnxruntime.

8810
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